Arindam Banerjee, Rajan Ghosh, Mainuck Das, Aniruddha Ghosh, Subham Ghosh and Samayita Sarkar, JIS College of Engineering, India

This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsatis an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.

MOSFET Scaling, Decremented, Multiplier, Factorial Design.